Field of the Disclosure
Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly to methods of fabricating fine geometry electrical circuits, such as 3D cross-point memory arrays.
Description of the Related Art
Semiconductor manufacturing of memory devices allows for high density to be achieved by constructing the arrays of data bits at very small geometries. The memory arrays include memory element layers and selector layers sandwiched between first metal layers and second metal layers, which run orthogonal the first metal layers. A single memory array may include a plurality of each of the aforementioned layers.
Because of the orthogonal orientation, memory arrays are traditionally constructed one layer at a time using a lithography step at each layer to rotate the pattern. Lithographic patterning, however, has its disadvantages. Lithography is the most costly step in a semiconductor manufacturing process, especially when those steps are for patterning the bit lines and words lines of a cross-point memory array at the finest geometry. Furthermore, each lithographic patterning step for each layer of final memory takes time and alignment of each of the layers takes additional time and may reduce overall yield.
Thus, there is a need in the art for an improved method for forming fine geometry electrical circuits, such as 3D cross-point memory arrays.